Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog
نویسندگان
چکیده
منابع مشابه
Multiplier-accumulator Using Radix-2 Modified Booth Algorithm and Spst Adder Using Verilog
In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 tr...
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Modular arithmetic operations (inversion, multiplication and exponentiation) are used in several cryptography applications. RSA and elliptic curve cryptography (ECC) are two of the most well established and widely used public key cryptographic (PKC) algorithms. The encryption and decryption of these PKC algorithms are performed by repeated modulo multiplications. These multiplications differ fr...
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ژورنال
عنوان ژورنال: International Journal of VLSI Design & Communication Systems
سال: 2012
ISSN: 0976-1527
DOI: 10.5121/vlsic.2012.3310